Flip chip packaging is broadly applied in consumer products such as smart phones, tablets, personal computers (PC), etc. to the supercomputer. Furthermore, it is predicted that the demand of flip chip packaging will increase sharply due to the appearance of three-dimensional lamination devices of the semiconductor chip using through-silicon via (TSV) technology.
In order to realize high performance in electronics devices, the pitch between bumps needs to be smaller. As a result, however, the potential for reliability problems, such as a crack, to arise in a bumping step or a packaging step becomes high as the bump's size and the pitch between bumps become smaller.
In the bumping step, a fine copper (Cu) pillar bump is generally formed by an electroplating method using a seed layer. In that case, when etching the seed layer undesirable undercutting of the Cu pillar or over etching of the sidewalls of the Cu pillar arises. FIG. 1 shows an example of undercutting and over etching of the Cu pillar bump which arises after etching of the seed layer. Therefore, there is a need for fine flip chip package technology, solving such problems.